1. Field of the Invention
This invention relates to high frequency oscillator circuits. More particularly, this invention relates to metal oxide semiconductor (MOS) oscillators having low phase noise.
2. Description of the Related Art
Inductive/capacitive (LC) oscillators are important elements of any Radio Frequency (RF) communication devices, such as transmitters, where the LC oscillators are used as master oscillators, or as receivers where the LC oscillators are used as local oscillators. An important performance benchmark of an LC oscillator is the phase noise characteristic. An oscillator with a lower phase noise indicates that the oscillator produces lower spurious energy outside the desired fundamental signal tone.
Phase noise is produced as a result of low frequency noise signal found in active elements used in the oscillator. This low frequency signal is modulated (up converted) by the fundamental signal tone, resulting in the spreading of the oscillator frequency energy beyond the intended target frequency. This low frequency noise signal source is often referred to as flicker noise (commonly referred to in the literature as 1/f) in bipolar and Metal Oxide Semiconductor (MOS) transistors. The 1/f noise energy in bipolar transistors is known to be significantly less than that of MOS transistors. This is the reason why practically all low phase noise LC oscillators are built using bipolar transistors or even more esoteric transistors such as Galium-Arsenide devices.
Complementary MOS (CMOS) based LC oscillators are now being investigated again for application to systems-on-a-chip (SOC) devices for RF communication applications. LC oscillators of the prior art fall far short of the minimum performance requirements of many of today's wireless communication systems.
A typical example of an LC oscillator in MOS technology is shown in FIG. 2. It is based on cross-coupled NMOS transistors M1 and M2, a pair of inductors L1 and L2, and capacitor C1 and C2 tuning elements. PMOS transistors, which usually have slightly lower 1/f noise characteristics, can be used to replace the NMOS transistors M1 and M2 at a slight increase in power dissipation and lower maximum operating frequency.
A review of a general form of the criteria for designing an oscillator circuit of the prior art is shown in FIG, 1. The necessary components of an oscillator are a frequency dependent gain circuit 100, a frequency dependent feedback circuit 105, and a combining block 110. The output V0 120 of the gain circuit 100 is the input to the feedback circuit 105. The input signal V1 115 is combined in the combining block 110 with the output Vfb 107 of the feedback circuit 105 to form the input 112 of the gain circuit 100.
The gain of the gain block 100 is designated G(jω) and the gain of the feedback circuit 105 is designated H(jω). These gains G(jω) and H(jω) describe the relationship of their respective output signals Vo 120 and Vfb 107 to their respective input signals 112 and Vo 120. Therefore, the output signal Vo 120 becomes       V    0    =                              V          1                ⁢                  G          ⁡                      (                          j              ⁢                                                           ⁢              ω                        )                                      1        +                              G            ⁡                          (                              j                ⁢                                                                   ⁢                ω                            )                                ⁢                      H            ⁡                          (                              j                ⁢                                                                   ⁢                ω                            )                                            .  
For an oscillator, the output signal Vo 120 must be nonzero even if the input voltage V1 115 is zero. For this to be true, then1+G(jω)H(jω)=0 or G(jω)H(jω)=−1. That is, the magnitude of the open-loop transfer function must be equal to 1 and the phase shift of the gain circuit 100 and the feedback circuit 105 must be 180°.
In FIG. 2, the gain circuit of the oscillator is formed by the differentially cross-connected pair of transistors M1 and M2 and the constant current source I1. The frequency dependent gain determining impedances are formed by the inductors L1 and L2 and the capacitors C1 and C2.
The feedback circuit is accomplished by the connecting of the drain of the NMOS transistor M1 to the gate of the NMOS transistor M2 and the drain of the NMOS transistor M2 to the gate of the NMOS transistor M1. This forms a cross-coupled differential oscillator.
A CMOS oscillator of the prior art is illustrated in FIG. 3. In this case, the gain circuit is formed by the differentially connected pair of NMOS transistors M1 and M2, the differentially connected pair of PMOS transistors M3 and M4, and the current sources I1 and I2. As described above, the frequency dependent gain determining impedances are formed by the inductors L1 and L2 and capacitors C1 and C2.
The fundamental frequency f0 of a cross coupled differential oscillator is determined by the formula:       ω    =                  1                                            L              eff                        ⁢                          C              eff                                          ⁢                           ⁢      such      ⁢                           ⁢      that                  f      0        =          1              2        ⁢        π        ⁢                                            L              eff                        ⁢                          C              eff                                                          where:                    Leff is the value of the effective inductance of the inductors L1 and L2.            Ceff is the value of the effective capacitance of the capacitors C1 and C2.For the structure of the design where the inductors are mutually coupled then the effective inductance is:Leff=4L1=4L2. The effective capacitance of the capacitors C1 and C2 is the parallel combination of the two capacitors C1 and C2 and is:Ceff=½C1=½C2Combining the above, the frequency of the oscillators of FIGS. 2 and 3 is:       f    0    =            1              2        ⁢        π        ⁢                              2            ⁢            L1C2                                .  It should be noted that the capacitances C1 and C2 included the parasitic capacitances of the oscillator circuit.                        
It is well known in the art that phase noise is the result of small perturbations in phase due to small random shifts in oscillator frequency. These shifts are caused by thermal noise, shot noise, and flicker noise (1/f noise). These noises are functions of the device characteristics of the NMOS transistors M1 and M2 of FIGS. 2 and 3 and the PMOS transistors M3 and M4 of FIG. 3. The phase noise is modeled as small voltage sources Vn1 and Vn2 at the gates of the NMOS transistors M1 and M2 of FIGS. 2 and 3 and voltage sources Vp1 and Vp2 at the gates of the PMOS transistors M4 and M4 of FIG. 3.
This flicker noise (1/f noise) is a function of the active device characteristics of the NMOS transistors M1 and M2 of FIGS. 1 and 2 and PMOS transistors M3 and M4 of FIG. 3.
The advancements in scaling of the device features in semiconductor processing allow multi-gigahertz operating frequencies to be readily achievable. Unfortunately, the same scaling down of MOS transistors have the opposite effect on the 1/f noise characteristics. The smaller device geometries are, the higher the 1/f noise components, leading to higher phase noise on the final oscillator.
“A 1.8 Ghz CMOS Voltage-Controlled Oscillator”, —Razavi, B., Digest of Technical Papers. 43rd ISSCC, 1997, pp. 388-389 and shown in FIG. 4 describes a structure of having multiple oscillators OSC1 and OSC2 coupled together to oscillate in quadrature or 90° out-of-phase. The oscillators OSC1 and OSC2 are structured and function as described in FIG. 2. The differential pair of NMOS transistors M3 and M4 and the current source I2 form a first coupling circuit. The first coupling circuit has an in-phase input that is formed by the gate of the NMOS transistors M3 and a out-of-phase input that is formed by the gate of the NMOS transistor M4. The first coupling circuit has a in-phase output that is formed by the drain of the NMOS transistor M4 and an out-of-phase output that is formed by the drain of the NMOS transistor M3. The in-phase input of the first coupling circuit is connected to the drain of the NMOS transistor M5 and the gate of the NMOS transistor M6. The out-of-phase input of the first coupling circuit is connected to the drain of the NMOS transistor M6 and the gate of the NMOS transistor M5. The in-phase output of the first coupling circuit is connected to the drain of the NMOS transistor M2 and the gate of the NMOS transistor M1. The out-of-phase output of the first coupling circuit is connected to the drain of the NMOS transistor M1 and the gate of the NMOS transistor M2.
The differential pair of NMOS transistors M7 and M8 and the current source I4 form a second coupling circuit. The second coupling circuit has an in-phase input that is formed by the gate of the NMOS transistors M7 and a out-of-phase input that is formed by the gate of the NMOS transistor M8. The second coupling circuit has a in-phase output that is formed by the drain of the NMOS transistor M8 and an out-of-phase output that is formed by the drain of the NMOS transistor M7. The in-phase input of the second coupling circuit is connected to the drain of the NMOS transistor M2 and the gate of the NMOS transistor M1. The out-of-phase input of the second coupling circuit is connected to the drain of the NMOS transistor M1 and the gate of the NMOS transistor M2. The in-phase output of the second coupling circuit is connected to the drain of the NMOS transistor M6 and the gate of the NMOS transistor M5. The out-of-phase output of the second coupling circuit is connected to the drain of the NMOS transistor M6 and the gate of the NMOS transistor M5.
The structure as shown generates two oscillatory signals, one between the drains of the NMOS transistors M1 and M2 and one between the drains of the NMOS transistors M5 and M6. The two oscillatory signals are in quadrature or 90° out of phase. The quadrature oscillator as described is subject to the phase noise problems as above-described.
“Design Issues In CMOS Differential LC Oscillators,” Hajimiri, A., Lee, T. H., IEEE Journal of Solid-State Circuits, pp. 717-724, May 1999 Vol. 34 Issue No. 5, presents an analysis of phase noise in differential cross-coupled inductance-capacitance (LC) oscillators. The effect of tail current and tank power dissipation on the voltage amplitude is shown. Various noise sources in the complementary cross-coupled pair are identified, and their effect on phase noise is analyzed.
“Phase Noise In CMOS Differential LC Oscillators”, Hajimiri, A., Lee, T. H., Digest of Technical Papers —1998 Symposium on VLSI Circuits, 1998, pp. 48-51, describes an analysis of phase noise in differential cross-coupled tuned tank voltage controlled oscillators. The effect of active device noise sources as well as the noise due to the passive elements is taken into account.
U.S. Pat. No. 5,475,345 (Gabara) teaches a CMOS coupled-tank oscillator having two inverters coupled, input-to-output, by inductances that may be simply wires, and a capacitance acting in parallel with each inverter that may be, simply, the inverter's gate capacitance.
U.S. Pat. No. 5,850,163 (Drost, et al.) discusses an active inductor oscillator with wide frequency range. The active inductor oscillator includes a tank circuit, buffer and integrating circuit that use differential transistor pairs that reduce phase jitter due to external common-mode noise sources.
U.S. Pat. No. 5,959,504 (Wang) describes a voltage controlled oscillator CMOS circuit using back gate terminals of CMOS transistors to vary the parasitic capacitances of the transistors. The back gate terminals receive a signal from a variable voltage source so that oscillation can be controlled by adjusting the variable voltage.
“A Low-Noise, 900-MHz VCO in 0.6-um CMOS” (Park, et al), IEEE Journal Of Solid-State Circuits, Vol. 34, pp. 586-591, May 1999, Issue No. 5, describes a low-noise, 900-MHz, voltage controlled oscillator (VCO) fabricated in a 0.6-um CMOS technology. The VCO consists of four-stage fully differential delay cells performing full switching. It utilizes dual-delay path techniques to achieve high oscillation frequency and obtain a wide tuning range.
“10 MHz CMOS OTA-C Voltage-Controlled Quadrature Oscillator,” Linares-Barranco, et al., IEEE Electronics Letters, June 1989, pp. 765-767, Vol. 25, Issue No. 12, details a quadrature-type voltage-controlled oscillator with operational transconductance amplifiers and capacitors (OTA-C).
“RC Sequence Asymmetric Polyphase Networks for RF Integrated Transceivers,” Galal et al, Transactions On Circuits And Systems —II: Analog And Digital Signal Processing, January 2000, pp. VOL 47, Issue No. 1, describes Resistance-Capacitance (RC) sequence asymmetric polyphase networks. A sequence of asymmetric polyphase networks provide the generation of highly matched wide-band quadrature signals which are immune to components mismatch, and suppression of the image signals without the need for highly selective RF filters and without employing image-reject mixing techniques.
U.S. Pat. No. 5,714,911 (Gilbert) describes a quadrature oscillator that includes an amplitude control circuit. The amplitude control circuit is that is based upon the trigonometric identity sin2(Ωt)+cos2(Ωt)=1. The amplitude control circuit, referred to as a Pythagorator, includes two squaring circuits. Each squaring circuit receives a respective quadrature oscillator signal and squares it. The outputs of the two squaring circuits are joined together so as to sum the outputs of the two squaring circuits to produce a sum of squares signal. This signal, a current in the preferred embodiment, is provided to damping diodes coupled to the outputs of the quadrature oscillator. The damping diodes produce a shunt positive resistance at the outputs of the quadrature oscillator in response to this current that has the effect of canceling the shunt negative resistance of the regenerative elements of the oscillator thereby establishing the amplitude of the quadrature oscillator signals at a desired amplitude.
U.S. Pat. No. 5,949,295 (Schmidt) teaches an integratable tunable resonant circuit for use in filters and oscillators. The circuit incorporates differential amplifier stage with a pair of differentially connected transistors with two negative feedback resistors. The two negative feedback resistors increase the linearity range of an input voltage of the differential amplifier stage.
U.S. Pat. No. 6,008,701 (Gilbert) details a quadrature oscillator using inherent nonlinearities of impedance cells to limit amplitude. The quadrature oscillator based on two cross-coupled integrator cells utilizing the inherent nonlinearity of positive and negative impedance cells to control the amplitude of oscillation. The oscillator is simplified thus eliminating the need for an outer control loop. A negative impedance cell is coupled to each integrator cell for assuring proper start-up and enhancing the amplitude of oscillation. A positive impedance cell is also coupled to each integrator cell to dampen the amplitude of oscillation. The transconductance of each impedance cell varies in response to the bias current provided to the cell. Thus, by controlling the bias currents through the cells, the negative and positive impedances seen by each integrator cell can made to cancel at the desired oscillation amplitude, so that the circuit oscillates without any damping or enhancement. By utilizing the inherent nonlinearity of positive and negative impedance cells, the bias currents provided to the impedance cells can remain fixed for a given frequency of operation, thereby simplifying the design of the oscillator and providing precise, robust control.